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ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
15 years 5 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
AINA
2010
IEEE
15 years 5 months ago
Mobile Element Path Planning for Time-Constrained Data Gathering in Wireless Sensor Networks
— We consider the problem of gathering data from a sensor network using mobile elements. In particular, we consider the case where the data are produced by measurements and need ...
Khaled Almiani, Anastasios Viglas, Lavy Libman
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
15 years 4 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak
ISPD
1999
ACM
127views Hardware» more  ISPD 1999»
15 years 4 months ago
Buffer insertion for clock delay and skew minimization
 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
X. Zeng, D. Zhou, Wei Li
DAC
1997
ACM
15 years 4 months ago
Wire Segmenting for Improved Buffer Insertion
Buffer insertion seeks to place buffers on the wires of a signal net to minimize delay. Van Ginneken [14] proposed an optimal dynamic programming solution (with extensions propose...
Charles J. Alpert, Anirudh Devgan