1768 search results - page 300 / 354 » Optimal routing in Chord |
DAC
2005
ACM
16 years 25 days ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
INFOCOM
2009
IEEE
15 years 6 months ago
2009
IEEE
—A significant fraction of network events (such as topology or route changes) and the resulting performance degradation stem from premeditated network management and operational...
DAC
2009
ACM
16 years 26 days ago
2009
ACM
As VLSI technology enters the nanoscale regime, interconnect delay has become the bottleneck of the circuit timing. As one of the most powerful techniques for interconnect optimiz...
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ICCAD
2004
IEEE
15 years 8 months ago
2004
IEEE
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...