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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 4 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
EUC
2005
Springer
15 years 3 months ago
Optimizing Nested Loops with Iterational and Instructional Retiming
Abstract. Embedded systems have strict timing and code size requirements. Retiming is one of the most important optimization techniques to improve the execution time of loops by in...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
INFOCOM
2000
IEEE
15 years 2 months ago
Near Optimal Routing Lookups with Bounded Worst Case Performance
Abstract—The problem of route address lookup has received much attention recently and several algorithms and data structures for performing address lookups at high speeds have be...
Pankaj Gupta, Balaji Prabhakar, Stephen P. Boyd
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
15 years 6 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
PLDI
1990
ACM
15 years 1 months ago
A Fresh Look at Optimizing Array Bound Checking
- This paper describes techniques for optimizing range checks performed to detect array bound violations. In addition to the elimination of range check:s, the optimizations discuss...
Rajiv Gupta