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» Optimal static range reporting in one dimension
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ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
15 years 6 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
WCRE
2007
IEEE
15 years 4 months ago
Interprocedural Static Single Assignment Form
In this paper we describe interprocedural static single assignment form (ISSA) with optimizations as implemented in the Bauhaus project. We explain our framework which abstract pr...
Stefan Staiger, Gunther Vogel, Steffen Keul, Eduar...
RTSS
2006
IEEE
15 years 3 months ago
Design of Location Service for a Hybrid Network of Mobile Actors and Static Sensors
Location services are essential to many applications running on a hybrid of wirelessly-networked mobile actors and static sensors, such as surveillance systems and the Pursuer and...
Zhigang Chen, Min Gyu Cho, Kang G. Shin
TSP
2008
134views more  TSP 2008»
14 years 9 months ago
A Mapping-Based Design for Nonsubsampled Hourglass Filter Banks in Arbitrary Dimensions
Multidimensional hourglass filter banks decompose the frequency spectrum of input signals into hourglass-shaped directional subbands, each aligned with one of the frequency axes. T...
Yue M. Lu, Minh N. Do
ICCAD
2006
IEEE
147views Hardware» more  ICCAD 2006»
15 years 6 months ago
Analysis and modeling of CD variation for statistical static timing
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao