862 search results - page 106 / 173 » Optimal task placement to improve cache performance |
ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
AROBOTS
2002
14 years 9 months ago
2002
Abstract. In multi-robot applications, such as foraging or collection tasks, interference, which results from competition for space between spatially extended robots, can significa...
INFOCOM
2010
IEEE
14 years 8 months ago
2010
IEEE
—Delay Tolerant Networks (DTN) are networks of self-organizing wireless nodes, where end-to-end connectivity is intermittent. In these networks, forwarding decisions are generall...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
CASCON
1996
14 years 11 months ago
1996
The trend in workstation hardware is towards symmetric shared-memory multiprocessors (SMPs). User expectations are for (largely) automatic exploitation of parallelismon an SMP, si...