862 search results - page 15 / 173 » Optimal task placement to improve cache performance |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
— One of the critical goals in code optimization for MPSoC architectures is to minimize the number of off-chip memory accesses. This is because such accesses can be extremely cos...
WISE
2003
Springer
15 years 2 months ago
2003
Springer
The efficient delivery of web content has been identified as a key issue of research for some time. Forward (or reverse) proxies, which are positioned along the request route from...
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Voted
TCAD
2010
14 years 4 months ago
2010
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract— The optimal size of a large on-chip cache can be different for different programs: at some point, the reduction of cache misses achieved when increasing cache size hits...
WSC
2004
14 years 11 months ago
2004
We investigate factors that impact the effectiveness of caching to speed up discrete event simulation. Walsh and Sirer have shown that a variant of function caching (staged simula...