862 search results - page 25 / 173 » Optimal task placement to improve cache performance |
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved perf...
DAC
2010
ACM
14 years 10 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance g...
100
Voted
JPDC
2010
14 years 8 months ago
2010
Non-uniform memory architectures with cache coherence (ccNUMA) are becoming increasingly common, not just for large-scale high performance platforms but also in the context of mul...