862 search results - page 30 / 173 » Optimal task placement to improve cache performance |
79
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
89
Voted
DSD
2010
IEEE
14 years 10 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
69
Voted
SIGGRAPH
1999
ACM
15 years 2 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
FAST
2010
15 years 11 hour ago
2010
Duplication of data in storage systems is becoming increasingly common. We introduce I/O Deduplication, a storage optimization that utilizes content similarity for improving I/O p...
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...