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» Optimal task placement to improve cache performance
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MICRO
2007
IEEE
115views Hardware» more  MICRO 2007»
15 years 4 months ago
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
Naveen Muralimanohar, Rajeev Balasubramonian, Norm...
SC
2009
ACM
15 years 4 months ago
Enabling software management for multicore caches with a lightweight hardware support
The management of shared caches in multicore processors is a critical and challenging task. Many hardware and OS-based methods have been proposed. However, they may be hardly adop...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
CASES
2007
ACM
15 years 1 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
LCN
2006
IEEE
15 years 3 months ago
Minimizing Cache Misses in an Event-driven Network Server: A Case Study of TUX
We analyze the performance of CPU-bound network servers and demonstrate experimentally that the degradation in the performance of these servers under highconcurrency workloads is ...
Sapan Bhatia, Charles Consel, Julia L. Lawall
KDD
1998
ACM
122views Data Mining» more  KDD 1998»
15 years 1 months ago
Memory Placement Techniques for Parallel Association Mining
Many data mining tasks (e.g., Association Rules, Sequential Patterns) use complex pointer-based data structures (e.g., hash trees) that typically suffer from sub-optimal data loca...
Srinivasan Parthasarathy, Mohammed Javeed Zaki, We...