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HIPEAC
2011
Springer
13 years 9 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
GECCO
2011
Springer
256views Optimization» more  GECCO 2011»
14 years 1 months ago
Evolving complete robots with CPPN-NEAT: the utility of recurrent connections
This paper extends prior work using Compositional Pattern Producing Networks (CPPNs) as a generative encoding for the purpose of simultaneously evolving robot morphology and contr...
Joshua E. Auerbach, Josh C. Bongard
USENIX
2007
15 years 3 days ago
Evaluating Block-level Optimization Through the IO Path
This paper focuses on evaluation of the effectiveness of optimization at various layers of the IO path, such as the file system, the device driver scheduler, and the disk drive i...
Alma Riska, James Larkby-Lahet, Erik Riedel
FAST
2008
15 years 3 days ago
Improving I/O Performance of Applications through Compiler-Directed Code Restructuring
Ever-increasing complexity of large-scale applications and continuous increases in sizes of the data they process make the problem of maximizing performance of such applications a...
Mahmut T. Kandemir, Seung Woo Son, Mustafa Karak&o...
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
15 years 2 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...