862 search results - page 61 / 173 » Optimal task placement to improve cache performance |
100
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ISCA
1996
IEEE
15 years 1 months ago
1996
IEEE
Memory latency is an important bottleneck in system performance that cannot be adequately solved by hardware alone. Several promising software techniques have been shown to addres...
117
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ECRTS
2009
IEEE
14 years 7 months ago
2009
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
122
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WMPI
2004
ACM
15 years 3 months ago
2004
ACM
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
ISCA
1999
IEEE
15 years 2 months ago
1999
IEEE
By optimizing data layout at run-time, we can potentially enhance the performance of caches by actively creating spatial locality, facilitating prefetching, and avoiding cache con...