862 search results - page 63 / 173 » Optimal task placement to improve cache performance |
ICDCS
2008
IEEE
15 years 4 months ago
2008
IEEE
The multi-level storage architecture has been widely adopted in servers and data centers. However, while prefetching has been shown as a crucial technique to exploit the sequentia...
CASES
2008
ACM
14 years 11 months ago
2008
ACM
Dynamic binary translators (DBT) have recently attracted much attention for embedded systems. The effective implementation of DBT in these systems is challenging due to tight cons...
RTAS
2005
IEEE
15 years 3 months ago
2005
IEEE
It is advantageous to perform compiler optimizations to lower the WCET of a task since tasks with lower WCETs are easier to schedule and more likely to meet their deadlines. Compi...
VTC
2010
IEEE
14 years 8 months ago
2010
IEEE
—We discuss a novel pilot design for multi-user channel estimation in the OFDM uplink with localized block-type pilot placement. Due to this placement, multiple users’ channels...
ECRTS
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper introduces improvements in partitioning schemes for multiprocessor real-time systems which allow higher processor utilization and enhanced schedulability by using exact...