Sciweavers

862 search results - page 72 / 173
» Optimal task placement to improve cache performance
Sort
View
ICML
2007
IEEE
15 years 10 months ago
Learning a meta-level prior for feature relevance from multiple related tasks
In many prediction tasks, selecting relevant features is essential for achieving good generalization performance. Most feature selection algorithms consider all features to be a p...
Su-In Lee, Vassil Chatalbashev, David Vickrey, Dap...
HPCA
1999
IEEE
15 years 2 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
JEC
2006
71views more  JEC 2006»
14 years 9 months ago
Destructive-read in embedded DRAM, impact on power consumption
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
Haakon Dybdahl, Per Gunnar Kjeldsberg, Marius Gran...
JCIT
2010
158views more  JCIT 2010»
14 years 4 months ago
A Flexible Grid Task Scheduling Algorithm Based on QoS Similarity
s In grid computing, the goals of task scheduling is to achieve high system optimization performance while matching multi-dimension Quiality of Service(QoS) requirement of applicat...
Kunfang Song, Shufen Ruan, Minghua Jiang
EUC
2006
Springer
15 years 1 months ago
Data-Layout Optimization Using Reuse Distance Distribution
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
Xiong Fu, Yu Zhang, Yiyun Chen