38 search results - page 1 / 8 » Optimal topology exploration for application-specific 3D arc... |
ASPDAC
2006
ACM
14 years 7 days ago
2006
ACM
DAC
2011
ACM
12 years 6 months ago
2011
ACM
In this work, we propose an efficient and accurate full-chip thermomechanical stress and reliability analysis tool and design optimization methodology to alleviate mechanical rel...
ICPP
2007
IEEE
14 years 17 days ago
2007
IEEE
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
DAC
2012
ACM
11 years 8 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
ICCD
2007
IEEE
14 years 3 months ago
2007
IEEE
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...