92 search results - page 17 / 19 » Optimal versus Heuristic Global Code Scheduling |
DAC
2000
ACM
15 years 10 months ago
2000
ACM
Memory delays represent a major bottleneck in embedded systems performance. Newer memory modules exhibiting efficient access modes (e.g., page-, burst-mode) partly alleviate this ...
CODES
2010
IEEE
14 years 6 months ago
2010
IEEE
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
107
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EUROPAR
2010
Springer
14 years 9 months ago
2010
Springer
Abstract. Limited bandwidth to off-chip main memory is a performance bottleneck in chip multiprocessors for streaming computations, such as Cell/B.E., and this will become even mor...
73
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LCPC
1998
Springer
15 years 1 months ago
1998
Springer
Techniques for aggressive optimization and parallelization of applications can have the side-effect of introducing copy instructions, register-to-register move instructions, into t...
ESCIENCE
2007
IEEE
15 years 4 months ago
2007
IEEE
The emergence of computational grids has lead to an increased reliance on task schedulers that can guarantee the completion of tasks that are executed on unreliable systems. There...