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133
Voted
ICCD
2007
IEEE
16 years 14 days ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
115
Voted
ICCD
2007
IEEE
16 years 13 days ago
2007
IEEE
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
115
Voted
ICCD
2006
IEEE
16 years 13 days ago
2006
IEEE
— Identifying performance bottlenecks is important for microarchitects and application developers to produce high performance microprocessor designs and application software. Man...
131
Voted
CVPR
2010
IEEE
15 years 11 months ago
2010
IEEE
When classifying high-dimensional sequence data, traditional methods (e.g., HMMs, CRFs) may require large amounts of training data to avoid overfitting. In such cases dimensional...
136
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EUROGRAPHICS
2010
Eurographics
15 years 11 months ago
2010
Eurographics
We present an approach to improve the search efficiency for near-optimal motion synthesis using motion graphs. An optimal or near-optimal path through a motion graph often leads ...