44 search results - page 5 / 9 » Optimality study of logic synthesis for LUT-based FPGAs |
FPGA
2007
ACM
15 years 3 months ago
2007
ACM
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
—When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve inj...
ISCAS
2006
IEEE
15 years 3 months ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...