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DATE
2009
IEEE
98views Hardware» more  DATE 2009»
15 years 7 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
HPCA
2006
IEEE
16 years 1 months ago
Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
115
Voted
GECCO
2004
Springer
152views Optimization» more  GECCO 2004»
15 years 6 months ago
A Hybrid Ant Colony Optimisation Technique for Dynamic Vehicle Routing
Abstract. This paper is concerned with a dynamic vehicle routing problem. The problem is dynamic in the sense that the time it will take to traverse each edge is uncertain. The pro...
Darren M. Chitty, Marcel L. Hernandez
99
Voted
ISCA
2005
IEEE
98views Hardware» more  ISCA 2005»
15 years 6 months ago
Techniques for Efficient Processing in Runahead Execution Engines
Runahead execution is a technique that improves processor performance by pre-executing the running application instead of stalling the processor when a long-latency cache miss occ...
Onur Mutlu, Hyesoon Kim, Yale N. Patt
118
Voted
ISLPED
1997
ACM
108views Hardware» more  ISLPED 1997»
15 years 5 months ago
Techniques for low energy software
The energy consumption of a system depends upon the hardware and software component of a system. Since it is the software which drives the hardware in most systems, decisions take...
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwi...