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FCCM
2000
IEEE
122views VLSI» more  FCCM 2000»
15 years 5 months ago
Evaluating Hardware Compilation Techniques
Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
Markus Weinhardt, Wayne Luk
GLVLSI
2009
IEEE
164views VLSI» more  GLVLSI 2009»
15 years 7 months ago
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...
111
Voted
LCTRTS
2007
Springer
15 years 7 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
VTS
2003
IEEE
81views Hardware» more  VTS 2003»
15 years 6 months ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara
75
Voted
DAC
2004
ACM
16 years 1 months ago
Profile-based optimal intra-task voltage scheduling for hard real-time applications
This paper presents a set of comprehensive techniques for the intratask voltage scheduling problem to reduce energy consumption in hard real-time tasks of embedded systems. Based ...
Jaewon Seo, Taewhan Kim, Ki-Seok Chung