Hardware compilation techniques which use highlevel programming languages to describe and synthesize hardware are gaining popularity. They are especially useful for reconfigurable...
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
This paper presents a set of comprehensive techniques for the intratask voltage scheduling problem to reduce energy consumption in hard real-time tasks of embedded systems. Based ...