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134
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DATE
2005
IEEE
133views Hardware» more  DATE 2005»
15 years 9 months ago
Locality-Aware Process Scheduling for Embedded MPSoCs
Utilizing on-chip caches in embedded multiprocessorsystem-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work th...
Mahmut T. Kandemir, Guilin Chen
ICS
2003
Tsinghua U.
15 years 8 months ago
Enhancing memory level parallelism via recovery-free value prediction
—The ever-increasing computational power of contemporary microprocessors reduces the execution time spent on arithmetic computations (i.e., the computations not involving slow me...
Huiyang Zhou, Thomas M. Conte
124
Voted
HPCA
2000
IEEE
15 years 8 months ago
Software-Controlled Multithreading Using Informing Memory Operations
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
Todd C. Mowry, Sherwyn R. Ramkissoon
153
Voted
MOBIDE
1999
ACM
15 years 8 months ago
Accelerating Telnet Performance in Wireless Networks
This paper describes the design of a system that significantly improves the performance of telnet data delivery for 3270 and 5250 emulation so that access to legacy applications v...
Barron C. Housel, Ian Shields
142
Voted
ASPLOS
1992
ACM
15 years 7 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta