5133 search results - page 150 / 1027 » Optimization in Object Caching |
145
Voted
ISLPED
2010
ACM
15 years 3 months ago
2010
ACM
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
140
Voted
JEC
2006
15 years 3 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
131
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ASPDAC
2009
ACM
15 years 1 months ago
2009
ACM
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
139
Voted
CODES
2001
IEEE
15 years 7 months ago
2001
IEEE
Comprehensive exploration of the design space parameters at the system-level is a crucial task to evaluate architectural tradeoffs accounting for both energy and performance const...
127
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ASPLOS
1987
ACM
15 years 7 months ago
1987
ACM
One potentialdisadvantage of a machine with a reduced instruction. set is that object programs may be substantially larger than those for a machine with a richer, more complex ins...