5133 search results - page 204 / 1027 » Optimization in Object Caching |
131
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IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
125
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DAMON
2007
Springer
15 years 10 months ago
2007
Springer
As XQuery rapidly emerges as the standard for querying XML documents, it is very important to understand the architectural characteristics and behaviors of such workloads. A lot o...
147
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IEEEPACT
2005
IEEE
15 years 9 months ago
2005
IEEE
Transactional Coherence and Consistency (TCC) is a novel coherence scheme for shared memory multiprocessors that uses programmer-defined transactions as the fundamental unit of p...
154
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ICDCSW
2003
IEEE
15 years 9 months ago
2003
IEEE
To obtain good performance in messaging over mobile networks, we have developed a Gateway. Gateway is a message hub that transmits information using store-and-forward messaging an...
106
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MICRO
2003
IEEE
15 years 9 months ago
2003
IEEE
Attacking bottlenecks in modern processors is difficult because many microarchitectural events overlap with each other. This parallelism makes it difficult to both (a) assign a ...