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FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
16 years 20 days ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
IWNAS
2008
IEEE
16 years 18 days ago
Software Barrier Performance on Dual Quad-Core Opterons
Multi-core processors based SMP servers have become building blocks for Linux clusters in recent years because they can deliver better performance for multi-threaded programs thro...
Jie Chen, William A. Watson III
DAMON
2007
Springer
16 years 12 days ago
Pipelined hash-join on multithreaded architectures
Multi-core and multithreaded processors present both opportunities and challenges in the design of database query processing algorithms. Previous work has shown the potential for ...
Philip Garcia, Henry F. Korth
APCSAC
2006
IEEE
16 years 8 days ago
A Study of the Performance Potential for Dynamic Instruction Hints Selection
Abstract. Instruction hints have become an important way to communicate compile-time information to the hardware. They can be generated by the compiler and the post-link optimizer ...
Rao Fu, Jiwei Lu, Antonia Zhai, Wei-Chung Hsu
IPPS
2005
IEEE
15 years 11 months ago
Automated Analysis of Memory Access Behavior
Abstract— We developed an automated environment to measure the memory access behavior of applications on high performance clusters. Code optimization for processor caches is cruc...
Michael Gerndt, Tianchao Li