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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 10 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
CGI
2000
IEEE
15 years 9 months ago
SQUEEZE: Fast and Progressive Decompression of Triangle Meshes
An ideal triangle mesh compression technology would simultaneously support the following three objectives: (1) progressive refinements of the received mesh during decompression, (...
Renato Pajarola, Jarek Rossignac
148
Voted
VISUALIZATION
1999
IEEE
15 years 9 months ago
Time-Critical Multiresolution Scene Rendering
We describe a framework for time-critical rendering of graphics scenes composed of a large number of objects having complex geometric descriptions. Our technique relies upon a sce...
Enrico Gobbetti, Eric Bouvier
WDAG
1994
Springer
104views Algorithms» more  WDAG 1994»
15 years 9 months ago
Fast Increment Registers
We give an optimal, wait-free implementation of an increment register. An increment register is a concurrent object consisting of an integer-valued register with an increment oper...
Soma Chaudhuri, Mark R. Tuttle
169
Voted
CCGRID
2007
IEEE
15 years 9 months ago
STORM: An Approach to Database Storage Management in Clustered Storage Environments
Database storage management in clustered storage environments is a manual, time-consuming, and error-prone task. Such management involves regular movement of database objects acro...
Kaushik Dutta, Raju Rangaswami