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ISCA
1993
IEEE
153views Hardware» more  ISCA 1993»
15 years 1 months ago
An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a writeinvalidate protocol result in invalidation actions that could be elimin...
Per Stenström, Mats Brorsson, Lars Sandberg
CLUSTER
2002
IEEE
15 years 2 months ago
Kernel-Level Caching for Optimizing I/O by Exploiting Inter-Application Data Sharing
With applications becoming larger and the increasing load on high performance systems, it is important to tackle the I/O bottleneck problem from several angles. It is not only ess...
Murali Vilayannur, Mahmut T. Kandemir, Anand Sivas...
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MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
15 years 1 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt
IEEEPACT
2009
IEEE
15 years 4 months ago
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors
Abstract—This paper proposes a new software-oriented approach for managing the distributed shared L2 caches of a chip multiprocessor (CMP) for latency-oriented multithreaded appl...
Lei Jin, Sangyeun Cho
IISWC
2008
IEEE
15 years 4 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood