5133 search results - page 81 / 1027 » Optimization in Object Caching |
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
GLVLSI
2008
IEEE
15 years 4 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
DAC
2009
ACM
15 years 2 months ago
2009
ACM
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
CCCG
2007
14 years 11 months ago
2007
We consider the problem of two-dimensional outputsensitive convex hull in the cache-oblivious model. That is, we are interested in minimizing the number of cache faults caused whe...
ERSA
2006
14 years 11 months ago
2006
The architecture and use of caches for two-level reconfigurable hardware is studied in this paper. The considered two-level reconfigurable hardware performs ordinary reconfiguratio...