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» Optimization of Collective Reduction Operations
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DAC
2005
ACM
15 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
70
Voted
ICCD
2003
IEEE
167views Hardware» more  ICCD 2003»
15 years 6 months ago
Virtual Page Tag Reduction for Low-power TLBs
We present a methodology for a power-optimized, software-controlled Translation Lookaside Buffer (TLB) organization. A highly reduced number of Virtual Page Number (VPN) bits sufï...
Peter Petrov, Alex Orailoglu
GLVLSI
2011
IEEE
351views VLSI» more  GLVLSI 2011»
14 years 1 months ago
Design of low-power multiple constant multiplications using low-complexity minimum depth operations
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
Levent Aksoy, Eduardo Costa, Paulo F. Flores, Jos&...
106
Voted
SIGMETRICS
2011
ACM
270views Hardware» more  SIGMETRICS 2011»
14 years 15 days ago
Scalable monitoring via threshold compression in a large operational 3G network
Threshold-based performance monitoring in large 3G networks is very challenging for two main factors: large network scale and dynamics in both time and spatial domains. There exis...
Suk-Bok Lee, Dan Pei, MohammadTaghi Hajiaghayi, Io...
FCCM
2005
IEEE
106views VLSI» more  FCCM 2005»
15 years 3 months ago
High-Performance FPGA-Based General Reduction Methods
FPGA-based floating-point kernels must exploit algorithmic parallelism and use deeply pipelined cores to gain a performance advantage over general-purpose processors. Inability t...
Gerald R. Morris, Ling Zhuo, Viktor K. Prasanna