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» Optimization of Collective Reduction Operations
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DAC
2003
ACM
15 years 10 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
15 years 3 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
CVPR
2007
IEEE
15 years 4 months ago
A Graph Reduction Method for 2D Snake Problems
Energy-minimizing active contour models (snakes) have been proposed for solving many computer vision problems such as object segmentation, surface reconstruction, and object track...
Jianhua Yan, Keqi Zhang, Chengcui Zhang, Shu-Ching...
FPGA
2008
ACM
174views FPGA» more  FPGA 2008»
14 years 11 months ago
Pattern-based behavior synthesis for FPGA resource reduction
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
Jason Cong, Wei Jiang
JCSC
2002
129views more  JCSC 2002»
14 years 9 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...