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» Optimization of Collective Reduction Operations
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SIGMOD
2003
ACM
140views Database» more  SIGMOD 2003»
15 years 9 months ago
The Design of an Acquisitional Query Processor For Sensor Networks
We discuss the design of an acquisitional query processor for data collection in sensor networks. Acquisitional issues are those that pertain to where, when, and how often data is...
Samuel Madden, Michael J. Franklin, Joseph M. Hell...
LCPC
1994
Springer
15 years 1 months ago
Optimizing Array Distributions in Data-Parallel Programs
Data parallel programs are sensitive to the distribution of data across processor nodes. We formulate the reduction of inter-node communication as an optimization on a colored gra...
Krishna Kunchithapadam, Barton P. Miller
71
Voted
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
15 years 3 months ago
Pre-synthesis optimization of multiplications to improve circuit performance
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
Rafael Ruiz-Sautua, María C. Molina, Jos&ea...
SIAMSC
2008
131views more  SIAMSC 2008»
14 years 9 months ago
Gramian-Based Model Reduction for Data-Sparse Systems
Model order reduction (MOR) is common in simulation, control and optimization of complex dynamical systems arising in modeling of physical processes and in the spatial discretizati...
Ulrike Baur, Peter Benner
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 6 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson