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» Optimization of Collective Reduction Operations
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CF
2009
ACM
15 years 4 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
MICRO
2007
IEEE
128views Hardware» more  MICRO 2007»
15 years 3 months ago
A Framework for Providing Quality of Service in Chip Multi-Processors
The trends in enterprise IT toward service-oriented computing, server consolidation, and virtual computing point to a future in which workloads are becoming increasingly diverse i...
Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer
CASES
2006
ACM
15 years 3 months ago
Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
Mark Hempstead, Gu-Yeon Wei, David Brooks
ICS
2004
Tsinghua U.
15 years 3 months ago
Adaptive incremental checkpointing for massively parallel systems
Given the scale of massively parallel systems, occurrence of faults is no longer an exception but a regular event. Periodic checkpointing is becoming increasingly important in the...
Saurabh Agarwal, Rahul Garg, Meeta Sharma Gupta, J...
HIPC
1999
Springer
15 years 1 months ago
Microcaches
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...
David May, Dan Page, James Irwin, Henk L. Muller