Sciweavers

96 search results - page 1 / 20
» Optimization of Combinational Logic Circuits Based on Compat...
Sort
View
DAC
1993
ACM
13 years 11 months ago
Optimization of Combinational Logic Circuits Based on Compatible Gates
Maurizio Damiani, Jerry Chih-Yuan Yang, Giovanni D...
DATE
2010
IEEE
183views Hardware» more  DATE 2010»
14 years 6 days ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
13 years 11 months ago
Optimal latch mapping and retiming within a tree
We propose a technology mapping algorithm that takes existing structural technology-mapping algorithms based on dynamic programming [1,3,4] and extends them to retime pipelined cir...
Joel Grodstein, Eric Lehman, Heather Harkness, Her...
CSREAESA
2003
13 years 8 months ago
Power Optimized Combinational Logic Design
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
R. V. Menon, S. Chennupati, Naveen K. Samala, Damu...
ASPDAC
1999
ACM
60views Hardware» more  ASPDAC 1999»
13 years 11 months ago
Timing Optimization of Logic Network Using Gate Duplication
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
Chun-hong Chen, Chi-Ying Tsui