96 search results - page 17 / 20 » Optimization of Combinational Logic Circuits Based on Compat... |
104
Voted
DAC
2004
ACM
15 years 4 months ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
121
Voted
TCAD
1998
15 years 1 days ago
1998
—This paper addresses, from a probabilistic point of view, the issue of switching activity estimation in combinational circuits under the zero-delay model. As the main theoretica...
101
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GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
74
Voted
ICCAD
1997
IEEE
15 years 4 months ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
94
Voted
HIPC
2004
Springer
15 years 5 months ago
2004
Springer
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to...