Sciweavers

104 search results - page 19 / 21
» Optimization of Industrial Applications with Hardware in the...
Sort
View
ISPASS
2010
IEEE
15 years 4 months ago
Runahead execution vs. conventional data prefetching in the IBM POWER6 microprocessor
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...
Harold W. Cain, Priya Nagpurkar
ISLPED
2004
ACM
88views Hardware» more  ISLPED 2004»
15 years 3 months ago
Architecting voltage islands in core-based system-on-a-chip designs
Voltage islands enable core-level power optimization for Systemon-Chip (SoC) designs by utilizing a unique supply voltage for each core. Architecting voltage islands involves isla...
Jingcao Hu, Youngsoo Shin, Nagu R. Dhanwada, Radu ...
FPGA
2003
ACM
137views FPGA» more  FPGA 2003»
15 years 2 months ago
Customized regular channel design in FPGAs
FPGAs are one of the essential components in platform-based embedded systems. Such systems are customized and applied only to a limited set of applications. Also some applications...
Elaheh Bozorgzadeh, Majid Sarrafzadeh
IEEEPACT
2006
IEEE
15 years 3 months ago
Compiling for stream processing
This paper describes a compiler for stream programs that efficiently schedules computational kernels and stream memory operations, and allocates on-chip storage. Our compiler uses...
Abhishek Das, William J. Dally, Peter R. Mattson
82
Voted
DAC
2008
ACM
15 years 10 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...