140 search results - page 5 / 28 » Optimization of high-performance superscalar architectures f... |
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...
167
Voted
PROCEDIA
2011
14 years 10 days ago
2011
Two decades of microprocessor architecture driven by quantitative 90/10 optimization has delivered an extraordinary 1000-fold improvement in microprocessor performance, enabled by...
ICCD
2005
IEEE
15 years 6 months ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses implemented in UDSM SoC Systems. Elimination or minimization of such faults is crucia...
102
click to vote
DAC
2004
ACM
15 years 1 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architecture...