Sciweavers

1404 search results - page 245 / 281
» Optimization problems in multiple-interval graphs
Sort
View
FCCM
2006
IEEE
107views VLSI» more  FCCM 2006»
15 years 3 months ago
Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
Uday Bondhugula, Ananth Devulapalli, James Dinan, ...
FOCS
2005
IEEE
15 years 3 months ago
Beyond VCG: Frugality of Truthful Mechanisms
We study truthful mechanisms for auctions in which the auctioneer is trying to hire a team of agents to perform a complex task, and paying them for their work. As common in the ï¬...
Anna R. Karlin, David Kempe, Tami Tamir
ASPDAC
2005
ACM
73views Hardware» more  ASPDAC 2005»
15 years 3 months ago
An-OARSMan: obstacle-avoiding routing tree construction with good length performance
- Routing is one of the important steps in VLSI/ULSI physical design. The rectilinear Steiner minimum tree (RSMT) construction is an essential part of routing. Since macro cells, I...
Yu Hu, Tong Jing, Xianlong Hong, Zhe Feng 0002, Xi...
GD
2005
Springer
15 years 3 months ago
Fast Node Overlap Removal
Most graph layout algorithms treat nodes as points. The problem of node overlap removal is to adjust the layout generated by such methods so that nodes of non-zero width and height...
Tim Dwyer, Kim Marriott, Peter J. Stuckey
61
Voted
DATE
2010
IEEE
127views Hardware» more  DATE 2010»
15 years 2 months ago
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis
— Pattern recognition has many applications in design automation. A generalized pattern recognition algorithm is presented in this paper which can efficiently extract similar pat...
Jason Cong, Hui Huang, Wei Jiang