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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 7 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
SOSP
2007
ACM
15 years 7 months ago
AjaxScope: a platform for remotely monitoring the client-side behavior of web 2.0 applications
The rise of the software-as-a-service paradigm has led to the development of a new breed of sophisticated, interactive applications often called Web 2.0. While web applications ha...
Emre Kiciman, V. Benjamin Livshits
SOSP
2009
ACM
15 years 7 months ago
The multikernel: a new OS architecture for scalable multicore systems
Commodity computer systems contain more and more processor cores and exhibit increasingly diverse architectural tradeoffs, including memory hierarchies, interconnects, instructio...
Andrew Baumann, Paul Barham, Pierre-Évarist...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
15 years 7 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
ASPLOS
2010
ACM
15 years 5 months ago
CoreDet: a compiler and runtime system for deterministic multithreaded execution
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
Tom Bergan, Owen Anderson, Joseph Devietti, Luis C...
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