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ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
16 years 1 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
16 years 1 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
16 years 1 months ago
A case for dynamic frequency tuning in on-chip networks
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
Asit K. Mishra, Reetuparna Das, Soumya Eachempati,...
ACNS
2009
Springer
123views Cryptology» more  ACNS 2009»
16 years 1 months ago
Practical Secure Evaluation of Semi-private Functions
Abstract. Two-party Secure Function Evaluation (SFE) is a very useful cryptographic tool which allows two parties to evaluate a function known to both parties on their private (sec...
Annika Paus, Ahmad-Reza Sadeghi, Thomas Schneider
ADHOCNOW
2009
Springer
16 years 1 months ago
Auction Aggregation Protocols for Wireless Robot-Robot Coordination
Abstract. Robots coordinate among themselves to select one of them to respond to an event reported to one of robots. The goal is to minimize the communication cost of selecting bes...
Ivan Mezei, Veljko Malbasa, Ivan Stojmenovic
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