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IPPS
2003
IEEE
15 years 10 months ago
Phylogenetic Tree Inference on PC Architectures with AxML/PAxML
Inference of phylogenetic trees comprising hundreds or even thousands of organisms based on the maximum likelihood method is computationally extremely expensive. In previous work,...
Alexandros Stamatakis, Thomas Ludwig 0002
116
Voted
ISCA
2003
IEEE
104views Hardware» more  ISCA 2003»
15 years 10 months ago
Token Coherence: Decoupling Performance and Correctness
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
Milo M. K. Martin, Mark D. Hill, David A. Wood
LCN
2003
IEEE
15 years 10 months ago
ReInForM: Reliable Information Forwarding Using Multiple Paths in Sensor Networks
Sensor networks are meant for sensing and disseminating information about the environment they sense. The criticality of a sensed phenomenon determines it’s importance to the en...
Budhaditya Deb, Sudeept Bhatnagar, Badri Nath
165
Voted
MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 10 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
151
Voted
MICRO
2003
IEEE
161views Hardware» more  MICRO 2003»
15 years 10 months ago
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers
In this paper we address the design of a future high-speed router that supports line rates as high as OC-3072 (160 Gb/s), around one hundred ports and several service classes. Bui...
Jorge García-Vidal, Jesús Corbal, Ll...
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