34170 search results - page 6494 / 6834 » Optimization |
139
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
152
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
139
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
DRAM vendors have traditionally optimized the cost-perbit metric, often making design decisions that incur energy penalties. A prime example is the overfetch feature in DRAM, wher...
157
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ISCA
2010
IEEE
15 years 9 months ago
2010
IEEE
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
145
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ITNG
2010
IEEE
15 years 9 months ago
2010
IEEE
—The plethora of applications for Wireless Sensor Networks (WSN) has experienced significant growth in recent years. Every application has a different set of requirements and it ...