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» Optimizations for LTL Synthesis
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97
Voted
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
14 years 10 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen
101
Voted
DAC
2006
ACM
16 years 1 months ago
Optimality study of resource binding with multi-Vdds
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu
75
Voted
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
15 years 4 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
110
Voted
ICCAD
1994
IEEE
117views Hardware» more  ICCAD 1994»
15 years 4 months ago
Optimization of critical paths in circuits with level-sensitive latches
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
Timothy M. Burks, Karem A. Sakallah
132
Voted
CVPR
2007
IEEE
16 years 2 months ago
Optimizing Binary MRFs via Extended Roof Duality
Many computer vision applications rely on the efficient optimization of challenging, so-called non-submodular, binary pairwise MRFs. A promising graph cut based approach for optim...
Carsten Rother, Vladimir Kolmogorov, Victor S. Lem...