894 search results - page 14 / 179 » Optimizations for LTL Synthesis |
FPGA
2006
ACM
15 years 2 months ago
2006
ACM
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
133
Voted
TOG
2012
13 years 1 months ago
2012
Current methods for combining two different images produce visible artifacts when the sources have very different textures and structures. We present a new method for synthesizing...
89
Voted
ICCAD
2001
IEEE
15 years 7 months ago
2001
IEEE
Timing closure problems occur when timing estimates computed during logic synthesis do not match with timing estimates computed from the layout of the circuit. In such a situation...
ASPDAC
2012
ACM
13 years 6 months ago
2012
ACM
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
ICCAD
1998
IEEE
15 years 3 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...