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» Optimizations for LTL Synthesis
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ISPD
2003
ACM
110views Hardware» more  ISPD 2003»
15 years 4 months ago
Explicit gate delay model for timing evaluation
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxi...
ICDT
2010
ACM
205views Database» more  ICDT 2010»
15 years 3 months ago
On the Aggregation Problem for Synthesized Web Services
The paper formulates and investigates the aggregation problem for synthesized mediators of Web services (SWMs). An SWM is a finite-state transducer defined in terms of templates...
Ting Deng, Wenfei Fan, Leonid Libkin, Yinghui Wu
FPL
2009
Springer
86views Hardware» more  FPL 2009»
15 years 3 months ago
Improving logic density through synthesis-inspired architecture
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
Jason Helge Anderson, Qiang Wang
DAC
2010
ACM
15 years 2 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
ICCS
2007
Springer
15 years 2 months ago
Building Verifiable Sensing Applications Through Temporal Logic Specification
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
Asad Awan, Ahmed H. Sameh, Suresh Jagannathan, Ana...