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» Optimizations for LTL Synthesis
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100
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ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
15 years 5 months ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
91
Voted
SIPS
2006
IEEE
15 years 5 months ago
Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format
—A wide variety of DSP design tools have been developed that incorporate dataflow graph representations into their GUI-based design environments. However, as the complexity of ap...
Ivan Corretjer, Chia-Jui Hsu, Shuvra S. Bhattachar...
85
Voted
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 4 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
76
Voted
CODES
2005
IEEE
15 years 4 months ago
Key research problems in NoC design: a holistic perspective
Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and ar...
Ümit Y. Ogras, Jingcao Hu, Radu Marculescu
102
Voted
ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
15 years 4 months ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan