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» Optimizations for LTL Synthesis
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103
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HPCA
2000
IEEE
15 years 4 months ago
Register Organization for Media Processing
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
Scott Rixner, William J. Dally, Brucek Khailany, P...
ICCAD
2000
IEEE
159views Hardware» more  ICCAD 2000»
15 years 4 months ago
ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters
A tool is presented that gives a high-level estimation of the power consumed by an analog continuous-time OTA-C filter when given only high-level input parameters such as dynamic ...
Erik Lauwers, Georges G. E. Gielen
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 4 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
103
Voted
ICCAD
1999
IEEE
120views Hardware» more  ICCAD 1999»
15 years 4 months ago
Regularity extraction via clan-based structural circuit decomposition
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
Soha Hassoun, Carolyn McCreary
109
Voted
FPGA
1999
ACM
142views FPGA» more  FPGA 1999»
15 years 4 months ago
Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems
Multi-FPGA systems are used as custom computing machines to solve compute intensive problems and also in the verification and prototyping of large circuits. In this paper, we addr...
Abdel Ejnioui, N. Ranganathan