894 search results - page 163 / 179 » Optimizations for LTL Synthesis |
104
Voted
ASPDAC
1998
ACM
15 years 3 months ago
1998
ACM
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
ASPDAC
2007
ACM
15 years 2 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
DAC
2010
ACM
15 years 2 months ago
2010
ACM
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address th...
110
Voted
ICCAD
2007
IEEE
15 years 2 months ago
2007
IEEE
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...
85
Voted
ASAP
2004
IEEE
15 years 2 months ago
2004
IEEE
Decreasing feature sizes allow additional functionality to be added to future microprocessors to improve the performance of important application domains. As a result of rapid gro...