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» Optimizations for LTL Synthesis
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GLVLSI
2006
IEEE
124views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Dominator-based partitioning for delay optimization
Most of the logic synthesis algorithms are not scalable for large networks and, for this reason, partitioning is often applied. However traditional mincut-based partitioning techn...
David Bañeres, Jordi Cortadella, Michael Ki...
84
Voted
ITC
1998
IEEE
114views Hardware» more  ITC 1998»
15 years 3 months ago
BETSY: synthesizing circuits for a specified BIST environment
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
Zhe Zhao, Bahram Pouya, Nur A. Touba
ISMVL
2010
IEEE
158views Hardware» more  ISMVL 2010»
15 years 2 months ago
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions
—Using EXOR gates in logic synthesis often results in smaller circuit realizations. While in AND/OR synthesis the problem definition is clear, in AND/EXOR synthesis several clas...
Alexander Finder, Rolf Drechsler
GECCO
2008
Springer
119views Optimization» more  GECCO 2008»
14 years 12 months ago
Evolutionary synthesis of low-sensitivity equalizers using adjacency matrix representation
An evolutionary synthesis method to design low-sensitivity IIR filters with linear phase in the passband is presented. The method uses a chromosome coding scheme based on the grap...
Leonardo Bruno de Sá, Antonio Carneiro Mesq...
ICCAD
1995
IEEE
114views Hardware» more  ICCAD 1995»
15 years 2 months ago
Sequential synthesis using S1S
Abstract—We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematical...
Adnan Aziz, Felice Balarin, Robert K. Brayton, Alb...