894 search results - page 18 / 179 » Optimizations for LTL Synthesis |
87
Voted
FMCAD
2008
Springer
15 years 13 days ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
GECCO
2008
Springer
14 years 12 months ago
2008
Springer
86
Voted
TVLSI
2010
14 years 5 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
DATE
2005
IEEE
15 years 4 months ago
2005
IEEE
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
94
Voted
DAC
2001
ACM
15 years 12 months ago
2001
ACM
Asynchronous design has been the focus of renewed interest. However, a key bottleneck is the lack of high-quality CAD tools for the synthesis of large-scale systems which also all...