894 search results - page 24 / 179 » Optimizations for LTL Synthesis |
80
Voted
ASPDAC
2008
ACM
15 years 28 days ago
2008
ACM
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
ICCAD
2000
IEEE
15 years 3 months ago
2000
IEEE
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
64
Voted
ICCD
2000
IEEE
15 years 3 months ago
2000
IEEE
In system-on-a-chip design, interfacing of Intellectual Property(IP) blocks is one of the most important issues. Since most IP’s are provided by different vendors, they have dif...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
High level synthesis transformations play a major part in shaping the properties of the final circuit. However, most optimizations are performed without much knowledge of the fina...
83
Voted
CCE
2006
14 years 11 months ago
2006
In this paper, we address the problem of optimal synthesis of an integrated water system, where water using processes and water treatment operations are combined into a single net...