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» Optimizations for LTL Synthesis
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ICCAD
1993
IEEE
134views Hardware» more  ICCAD 1993»
15 years 3 months ago
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs
In this paper, we present an integrated approach to synthesis and mapping to go beyond the combinatorial limit set up by the depth-optimal FlowMap algorithm. The new algorithm, na...
Jason Cong, Yuzheng Ding
TNN
1998
132views more  TNN 1998»
14 years 10 months ago
Synthesis of fault-tolerant feedforward neural networks using minimax optimization
—In this paper we examine a technique by which fault tolerance can be embedded into a feedforward network leading to a network tolerant to the loss of a node and its associated w...
Dipti Deodhare, M. Vidyasagar, S. Sathiya Keerthi
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
15 years 5 months ago
System level clock tree synthesis for power optimization
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
Saif Ali Butt, Stefan Schmermbeck, Jurij Rosenthal...
JPDC
2006
117views more  JPDC 2006»
14 years 11 months ago
Efficient synthesis of out-of-core algorithms using a nonlinear optimization solver
We address the problem of efficient out-of-core code generation for a special class of imperfectly nested loops encoding tensor contractions arising in quantum chemistry computati...
Sandhya Krishnan, Sriram Krishnamoorthy, Gerald Ba...
ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
15 years 3 months ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen