894 search results - page 34 / 179 » Optimizations for LTL Synthesis |
DMTCS
2002
14 years 10 months ago
2002
98
Voted
ICCAD
2010
IEEE
14 years 9 months ago
2010
IEEE
JCP
2008
14 years 11 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
DATE
2003
IEEE
15 years 4 months ago
2003
IEEE
In this paper, a simulation-based synthesis tool, AMIGO, for analog cell sizing is presented. AMIGO is based upon genetic optimization techniques adapted to circuit sizing. A fram...
DATE
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper presents a new approach to cross-level hierarchical high-level synthesis. A methodology is presented, that supports the efficient synthesis of hierarchical specified sy...